Information exchange between locally synchronous circuits

ABSTRACT

A locally synchronous circuit module has a delay circuit having and input and output coupled to a clock input. The delay circuit provides a delay which when incorporated in a clock oscillator ensures a clock period that is at least as long as needed to transfer information between the storage elements. A handshake circuit is provided for generating handshake signals for timing information transfer between the locally synchronous circuit module and a further circuit. The handshake circuit comprises the delay circuit, so that at least part of the handshake signals during a handshake transaction are timed by traveling through the delay circuit and are applied to the clock input to clock the locally synchronous circuit module.

The invention relates to a digital electronic circuit with one or morelocally synchronous circuit modules.

From a publication by J. Muttersbach, T. Villiger and W. Fichtner,titled “Practical Design of Globally Asynchronous Locally SynchronouusSystems and published in the Proceedings of the international symposiumon advanced research in asynchronous circuits and systems, April 2000,pages 52–59 it is known to provide communication between a number oflocally synchronous circuit modules.

Most present day circuits are synchronous circuits in which internaldata transport between all different registers (possibly via sequentiallogic circuits) is timed by a single central clock signal or a pluralityof synchronized clock signals. For various reasons it is desirable toswitch to architectures with a plurality of such synchronous circuitmodules, each operating under control of its own clock signal, the clocksignals of the different circuits being asynchronous from one another.Thus, each circuit modules is locally synchronous, but the differentmodules operate asynchronously from one another.

In such circuits with locally synchronous modules a problem arises wheninformation needs to be exchanged between different modules. Because theclock signals of the different modules are not synchronized, thedifferent modules cannot be connected without further measures. It isnecessary to provide interface circuits to guarantee that a module thatoutputs information does not change that information when another moduleneeds the information to be constant in order to read the information.

The article by Muttersbach et al. discloses a circuit that implementsthe interface circuits by means of a pausable clock. When informationneeds to be exchanged between a first and second module the clocks ofthese modules are temporarily stopped. While the clocks are stopped aconventional asynchronous handshake is used to transfer the information.The asynchronous handshake uses two signals: a request signal from thefirst module to the second module to indicate when the information is aavailable and an acknowledge signal from the second module back to thefirst module to indicate when the information has been received.

The pausable clock circuits of Muttersbach et al. each comprise anarbiter (a mutual exclusion element) and an inverting delay line whoseoutput is coupled to its input via the arbiter. A feedback from theoutput of the delay line to its input causes the generation of clockpulses. The input signal of the delay line is fed to the locallysynchronous circuit as a clock signal. The pausable clock circuitensures that the active part of the clock signal (the clock pulse,during which the clock is high) always has the same length. The passivepart (clock low) can be extended when the clock is paused. Clockglitches (shorter times between clock transitions) are prevented. Thearbiter ensures that handshake signals are only exchanged when the clocksignal is passive (low). However, the arbiter has the disadvantage thatit can cause unpredictable delays in case of metastability.Metastability occurs when transitions at the inputs of the arbiter occurnearly simultaneously. In this case it can take a long time before oneof the signals is passed.

The circuit of Muttersbach et al. requires a register between themodules that exchange information, for temporarily storing theinformation. This is because the handshake is executed while the clockis passive, so that the modules themselves cannot change or receive dataduring the handshake. The register causes circuit overhead in thecircuit and it delays the response time of the circuit.

Amongst others, it is an object of the invention to provide for acircuit with locally synchronous circuit module in which the clock inputto the locally synchronous circuit module does not need to be madepassive during exchange of data between the locally synchronous circuitmodule and further circuits.

Amongst others, it is another object of the invention to provide for acircuit with locally synchronous modules in which no register is neededduring information exchange between the modules.

Amongst others, it is another object of the invention to provide for acircuit with locally synchronous modules in which the use of circuitsthat suffer from metastability problems is minimized.

The circuit according to the invention is set forth in claim 1.According to the invention the delay line in the oscillator circuitsremains an active part of the circuit during information exchangebetween the locally synchronous modules. During the exchange thecoupling from the output of the delay line to its input is rerouted sothat the delay line participates in generating handshake signals whichalso act as clock signals for the locally synchronous modules.

In an embodiment of the circuit according to the invention the couplingbetween the output of the delay line and its input is routed through alocal path so that the clock signals are generated autonomously as longas the locally synchronous circuit module does not need to exchangeinformation with the further circuit. When information has to beexchanged the coupling is rerouted to create a handshake circuit. Thus,the locally synchronous circuit module can operate at maximum speed whenno exchange of information is needed.

In a further embodiment the information is exchanged using temporallyoverlaid information exchange transactions, for example by sendingsuccessive commands and returning responses to each command while asubsequent command is sent. When a last command has been sent adifferent operation occurs in that a response needs to be received whilenot sending a subsequent command. In this embodiment the couplingbetween the output of the delay line and its input is rerouted throughthe local path when the last command has been sent, but the local pathis disabled until the last response has been received. Thus, theexchange of information is properly timed and it is avoided that thetiming of new commands is triggered. This can be applied advantageouslyto reading of data from a memory, where the data for one address isreturned when a next address is applied. According to the embodiment nonext memory cycle needs to be started by the handshake interface toreceive the data.

In a further embodiment it is possible to overrule the disablingdependent on the command. Thus, if no response is needed the clock canoperate at maximum speed immediately, without waiting for the response.In the case of memory access, for example, in this way the clock canoperate at high speed immediately after a write operation, and can bedelayed after a read operation, when data needs to be returned frommemory.

In another embodiment, a plurality of further circuits is provided,which may operate asynchronously from one another. For this case ademultiplexer is provided which allows selection from a plurality ofcouplings to couple the output of the delay line to its input. Differentones of the couplings provide for generating handshakes with differentones of the further circuits.

In another embodiment a plurality of locally synchronous circuit modulesis provided, which share access to the further circuit. In this casehandshakes from the further circuit may be exchanged with any of thelocally synchronous circuit modules. An arbiter is used to arbitrate towhich of the locally synchronous circuit modules the handshake goes.Thus multiple locally synchronous circuit modules can share access tothe further circuit. In an embodiment, the locally synchronous modulecan reroute the coupling between the output and input of its delay lineeither locally or in synchonism with the arbiter. Thus the locallysynchronous module can operate at maximum speed when it does not need toaccess memory and its clock signal is delayed by a minimum amount whenit accesses memory. In a further embodiment the further circuit is amemory and an exchange module is included to make the arbiter in frontof the memory appear as if it was an unshared memory. Thus the locallysynchronous circuit modules, the locally synchronous circuit module areminimally delayed by the fact that they share the same memory. In anembodiment write operations need not wait for the return of data fromthe shared memory.

Of course the locally synchronous circuit module may be incorporated inan integrated circuit with its delay line and handshake interface. Thefurther circuits with which the locally synchronous circuit modulecommunicates may be included in the same integrated circuit, or they maybe provided in separate integrated circuits that can be connected to theintegrated circuit with the locally synchronous circuit module.

These and other advantageous aspects of the circuit according to theinvention will be described in more detail using the following Figures.

FIG. 1 shows a circuit-with a locally synchronous module;

FIG. 2 shows a locally synchronous module with a rerouting circuit;

FIG. 3 a handshake demultiplexer;

FIG. 4 shows a locally synchronous module and a memory;

FIG. 5 shows signals occurring during the exchange of information;

FIG. 6 shows a locally synchronous module with a memory;

FIG. 7 shows a locally synchronous module with a plurality of memories;

FIG. 8 shows a plurality of circuit modules with a shared secondcircuit; and

FIG. 9 shows an exchange module.

FIG. 1 shows a circuit with a first circuit 10, a second circuit 12, ahandshake interface circuit 14 and an interface 16 for informationexchange. The first circuit 10 comprises a locally synchronous circuitmodule 100 and a clock circuit 102. Locally synchronous circuit module100 comprises a plurality of registers 108 and logic and/or arithmeticcircuitry 109. Outputs of the registers 108 are coupled to inputs of theregisters 108 via logic and/or arithmetic circuitry 109. This connectionmay form a pipe-line containing successively different ones of theregisters 108 at successive stages of the pipe-line and/or loops inwhich an output of one or more of the registers 108 is fed back,directly or indirectly to its inputs.

The clock circuit 102 is coupled to a clock input 106 for clockingregisters 108. The clock circuit 102 comprises an inverting delay line104 (implemented for example as a cascade of an odd number ofinverters). An input of the delay line 104 is coupled to the clock input106.

Registers 108 from locally synchronous circuit module 100 are coupled tothe second circuit 12 via interface 16 for information exchange (ifnecessary sequential logic circuits may be included in the coupling).The input and output of the inverting delay line 104 of first circuit 10are coupled to the second circuit 12 via handshake interface.

In operation locally synchronous circuit module 100 is designed as aconventional synchronous circuit. That is, during operation theplurality of registers 108 is clocked via a common clock input 106, soas to load data output from the registers 108 directly, or afterintermediate processing by logic and/or arithmetic circuitry 109. Inprinciple, there will be many different paths through which data flowsfrom registers 108 in parallel back to the registers 108. Each path mayneed a different time interval to propagate the data from the registers108 back to the registers 108. The clock period with which the registers108 can be clocked should exceed a minimum allowable duration, whichcorresponds to the maximum time interval needed for any data topropagate from the registers 108 back to the registers and the timeneeded by registers 108 to set up and load data. The delay line 104produces a delay which corresponds to this minimum allowable duration.Therefore, if the input of the delay line 104 would be coupled to itsoutput, the delay line would generate a clock oscillation with therequired clock period.

The delay line 104 is coupled to the handshake interface 14 so as tosynchronize the clock oscillation of the clock circuit 102 withhandshakes from second circuit 12. This allows data to be exchanged withsecond circuit 12. A rising signal edge at the output of inverting delayline 104 is treated as a request Creq for data transfer and passed tosecond circuit 12. During data transfer from first circuit 10 to secondcircuit 12 for example, the data to be transferred will be output byregisters 108 and stable on the information exchange interface 16between first circuit 10 and second circuit 12. When second circuit 12indicates that the request is accepted (for example when the data hasbeen loaded into second circuit) an acknowledge signal Cack is passedback from second circuit 12 to the input of the delay line 104, causingthe delay line 104 to change back the Creq signal after a delay. Thefall in the Creq signal indicates to second circuit 12 that firstcircuit 10 has removed the data from the interface. When second circuit12 in turn indicates that new data may be placed on the interface 16 theacknowledge signal Cack is pulled low, causing the delay line 104 tochange back the Creq signal after a delay and so on. Thus, the delayline 104 is operated as a clock for locally synchronous circuits 100 andat the same time as a handshake interface towards second circuit 12.

It will be understood that, although this mechanism has been describedin terms of data transfer from first circuit 10 to second circuit 12,the mechanism applies as well to data transfer from second circuit 12 tofirst circuit 10.

FIG. 2 shows the first circuit 10, with locally synchronous circuit 100and clock circuit 102 coupled to a multiport handshake interface 20. Thelocally synchronous circuit module 100 has a select output Se1 coupledto the multiport handshake interface 20. The multiport handshakeinterface 20 contains a handshake demultiplexer 22, with a control inputcoupled to the Se1 output of locally synchronous circuit module 100, andwith a first port and a plurality of second ports 24 a–c, 26. The firstport is coupled to the input and output of delay line 104. A number ofthe second ports 24 a–c is coupled to respective handshake interfaces 14which in turn may be coupled to various further circuits (not shown)capable of handshake interfacing, such as the second circuits. One ofthe second ports 26 has a request output and an acknowledge inputcoupled to each other.

In operation demultiplexer 22 functions to provide a coupling from theoutput of delay line 104 to the input of the delay line 104 via aselected one of the second ports 24 a–c, 26. That is, demultiplexer 22routes a signal between its first port to a selected one of the secondports 24 a–c, 26. The second port 24 a–c, 26 is selected under controlof the control input se1. When locally synchronized circuit module 100does not need to exchange information with other circuits that are notlocally synchronous with it, the connection between the input and outputof delay line 104 is routed through the port 26 that connects therequest output and acknowledge input of that port directly. Thus,oscillator circuit 102 is made to oscillate basically as a ringoscillator at a maximum possible clock frequency at which locallysynchronous circuit module 100 can operate.

When locally synchronous circuit module 100 has to communicate viainterface 16 it directs demultiplexer 22 to reroute the coupling betweenthe input and the output of the delay line 104 via another one of theports, selected according to the circuit (not shown) with which theinformation has to be communicated. In that case the output signals ofthe delay line 104 will lead to input signals of the delay line via ahandshake interface 14 to the relevant port. Thus the period of theclock signal applied to the locally synchronous circuit 100 willgenerally be lowered, so as to adapt to the speed of informationexchange.

FIG. 3 shows an implementation of a demultiplexer with two second portsin more detail. The demultiplexer contains a first and second latch 30,32, a first and second AND gate 34, 36 and an OR gate 38. The Creqoutput of the delay line 104 of processor 10 is coupled to clock inputsof the latches 30, 32 and to first inputs of the AND gates 34, 36. These1 output of the synchronous module 100 of the processor 10 is coupledto the data inputs of the latches 30, 32, via an inverting and anon-inverting input respectively. The data outputs of the latches 30, 32are coupled to the outputs (Req1, Req2) of the second ports of thedemultiplexer 140. The latches 30, 32 are of a transparent-low typewhich passes the se1 signal (or its inverse) when the Creq is low andholds the last value of se1 (or its inverse) when Creq is high. Theinputs Ack1, Ack2 of the second ports are coupled to the inputs of ORgate 38. The output of OR gate 38 is coupled to the input Cack of thedelay line and the input Creq of the processor 10 and the clock input ofthe synchronous module 100. It will be understood that if a greaternumber of ports is required a correspondingly greater number of latches30, 32 may be provided, each latching a respective se1 signal for arespective port. The respective se1 signals may be obtained by using amulti-line se1 output from first circuit 10, for example with lines foreach port.

In operation locally synchronous circuit module causes a change in thelogic level of control signal se1 at a time when Creq is high. As aresult the new value of se1 is passed to AND gates 34, 36 once Creqbecomes low. Subsequently one of the AND gates 34, 36 passes the CReqsignal to a corresponding output CReq1, Creq2, the other AND gateblocking the Creq signal, keeping its output Creq1, Creq2 low. Low tohigh transitions on any of the acknowledge inputs Ack1, Ack2 are passedto the acknowledge output Cack of the first port.

FIG. 4 shows a circuit in which locally synchronous circuit module 100is part of a processor 10 communicating with a memory 12. Although asingle memory 42 is shown memory 42 may in fact comprise a number ofmemory devices that operate in synchronism with one another and/ormemory 42 may contain a cache structure. The circuit of FIG. 4 is anspecific application of the circuit as shown in FIG. 2. In additionspecial measures have been taken in the handshake interface to allow theuse of conventional memory and processor design. Such designs providefor pipelined read operations, in which an address is applied to thememory in one clock cycle and the resulting data is returned later,while at the same time a subsequent address is applied to the memory.

The circuit of FIG. 4 contains memory 42 and a handshake interface 44.The memory 42 has an access/data data interface coupled to processor 10(the access part of the interface provides for transfer of addresses andoptional further signals such as read/write control signals). The memory42 has a memory ready output “Ready” fed back to a memory request inputMreq via handshake interface 44. Handshake interface 44 contains ahandshake demultiplexer 440, a Muller C element 442 and an AND gate 444.The known Muller C element is designed to output a logic one or a logiczero when both its input signal are logic one or logic low respectivelyand to retain its prior output signal value when the input signalsdiffer.

The demultiplexer 440 has a first port coupled to the input Cack andoutput Creq of the delay circuit 104 of the oscillator of the processor10. The demultiplexer has a second port A (access port) and third port S(skip port) each with input (Aack, Sack) and an output (Sreq, Sack). Thedemultiplexer 440 has a control input se1 fed by the synchronous circuit100 of the processor 10.

In operation processor 10 has two modes of operation, a first mode inwhich memory 12 is not accessed and a second mode in which memory 12 isaccessed. In the first mode synchronous module 100 outputs the controlsignal se1 so as to command demultiplexer 440 to coupled the first port(Creq, Cack) and the third port A (Sreq, Sack). Thus, the output Creqand the input Cack of the delay line 104 are coupled via AND gate 444.Normally the ready signal from memory 12 is high so that the AND gate144 simply passes the signal from Creq to Cack. As a result, anoscillation occurs in which Creq and Cack are alternately logic high andlogic low, and produce a clock signal for synchronous module 100. Thedelay of delay line 104 is designed so that the aggregate delay causedby the cascade of delay line 104, demultiplexer 440 and AND gate 444leads to clock periods that are at least as long as any delay periodneeded to pass data between registers in locally synchronous circuitmodule 100.

When locally synchronous circuit module 100 has to access memory 12 itcauses interface circuit 44 to reroute the coupling from the output Creqof delay line 104 to the input Cack of delay line 104. Instead ofpassing through AND gate 444, this coupling is now made to pass throughMuller C-element 442. As a result a common oscillator circuit comes intoexistence, which generates one or more clock pulses for both processor10 and memory 12, to time the transfer of information such as addressesand data between the processor 10 and the memory 12. In case of a memoryread operation synchronous module 100 keeps this coupling through theMuller C element 142 during the exchange of address and subsequent data.During a write operation the coupling needs to be maintained only duringa simultaneous exchange of address and data information.

FIG. 5 shows signals occurring during memory access in more detail.First of all, during a memory read operation, initially in the firstmode, the output Areq of the second port A of the demultiplexer 440 islogic low. At the start of memory access synchronous module 100 appliesan address (and optionally data) to memory 42 via the access/datainterface and causes a change 50 in the logic level of control signalse1 at a time when Creq is high. As a result the new value of se1 ispassed to AND gates 34, 36 once Creq becomes low. Subsequently Sreqremains low as long as se1 keeps this value.

The next low to high transition 52 of Creq is passed to the output Areqof the demultiplexer 140. Since “ready” is high this leads to a low tohigh transition 54 on Mreq, Aack (shown collectively as Mreq) and Cack.This transition 54 starts a next clock cycle in synchronous module 100and signals to memory 42 that access information, including an addressand, optionally, data, is available and that a memory operation usingthis information is required. In this clock cycle synchronous module 100changes back se1 again to reroute the feed-back part of the clockoscillator on the next edges of Creq demultiplexer 440 so thatsubsequent transitions of Creq are passed via AND gate 444.

Memory 42 responds to the rising edge on Mreq by making “ready” low toindicate that the information from processor 10 has been received. Aftera delay determined by inverting delay circuit 104 the rising edge 54 onCack leads to a falling edge 56 on Creq and Areq. The changed value ofse1 is now passed to AND gates 34, 36. When ready and Aack are low theMuller C element 442 makes MReq, Aack and Cack go low, terminating theactive part of the clock cycle. It will be appreciated that the time atwhich Mreq goes low depends on whichever of Areq (Creq) and ready goeslow latest, i.e. that the time interval over which MReq, Aack and Cackare high may be longer that the delay caused by delay circuit 104.

In response to the low value of Cack delay circuit 104 will cause a lowto high transition 58 in Creq and Sreq after a delay determined by delaycircuit 104. Memory 42 will cause a low to high transition 59 in “ready”when data has become available upon reading. Usually the time intervalup to this transition 59 is much longer than the delay caused by delaycircuit 104. When both Sreq and “ready” are high AND gate 144 makes Sackand Cack go high. This clocks synchronous module 100, causing it to loadthe data from memory 42. Because ready is now high and se1 is back atits original level the frequency of the clock signal generated for thesynchronous module 100 no longer depends on delays determined by memory42. Thus synchronous module 100 returns to high speed operation with itsown local clock pulses until a next memory read operation is needed.

When synchronous module 100 has to execute a series of successive readoperations it may keep se1 unchanged at the level reached at the startof the first operation. Thus in response to each low to high transitionof the “ready” signal a next Mreq pulse will be generated (assuming thememory 42 to be slower than the processor 10). During each next Mreqpulse processor 10 supplies a new address to the access/data interfacesimultaneously with receiving data for a previous address, if thatprevious address was involved in a read operation.

The data received in response to the last address (or the only addressin case of a single read operation) is received when the demultiplexer440 already routes signals between the output and input of invertingdelay line 104 via the third port S. Because AND gate 444 is attached tothis port S the low to high transition from the output Creq of the delayline 104 will be passed back to the input Cack of the delay line 104only when the “ready” signal has gone high. Thus, it is ensured that thefirst pulse that travels via third port S is passed only when data isavailable. Because second port A is not used to ensure a delay untildata is available no new Mreq pulse is generated so that memory 42remains in a ready state for receiving a next address. Of coursemultiple access operation can also be realized by changing the logiclevel of se1 back and forth for each access operation.

In principle clock pulses for write operations can be generated in thesame way as for read operations. In this case, the processor 10 waitsuntil the data has been stored in memory 12, and the processor clock isdelayed until storing has been completed. However, in an embodimentprocessor 10 does not wait for completion of writing but resumesoperation at full speed during the time that memory 12 is still busystoring the data.

FIG. 6 shows a modified circuit that supports this type of operation. Inaddition to the components shown in FIG. 4, the circuit of FIG. 6contains an additional AND gate 64, a read flipflop 62 and an OR gate60. The additional AND gate 64 receives the se1 signal and a read/writecontrol signal from the interface between processor 10 and memory 42.The output of the additional AND gate 64 is coupled to the data input ofthe read flipflop 62. The read flipflop 62 is clocked by the rising edgeof Cack. The data output of the read flipflop 62 is coupled to OR gate60 together with the ready output from memory 42. The output of the ORgate 60 is coupled to AND gate 444 that passes Sreq to Areq for thethird port.

Thus, the direct coupling of the ready signal to AND gate 444 isreplaced by an indirect coupling that forces the input of AND gate 444high unless there has been a read operation. Thus, low to hightransitions on Sreq (caused by low to high transitions on Creq) aredelayed only in case of the read operation. In case of a write operationthe first pulse via third port S after access to memory 42 is as fast asany other pulse passed via third port S. In case of a read operationthis first pulse is delayed until memory 42 is ready.

The explanation of FIGS. 4 and 6 assume a “one-deep” memory pipe-line,i.e. they assume that data is for an address is delivered from memoryone cycle after applying the address. Of course a deeper pipelinedmemory may be used, which delivers data a greater number of cycles afteraccess. In this case, pipelined data remains in memory 42. When theprocessor 10 needs to perform isolated read actions it must keep thesecond port A selected for a sufficient number of cycles for memory 42to produce the data. Similarly the explanation has assumed that onlyduring a single cycle data is passed in conjunction with an address. Ifmore than one successive cycle is used the processor may keep the secondport A selected for a number of cycles for memory 42 after supplying theaddress.

A number of memories that operate asynchronously from one another may beused in parallel with memory 42. In this case, the acknowledgement ofrequests Creq by processor 10 may be controlled by those memories thatare accessed and those that have to deliver data. This may be realizedfor example by using a correspondingly greater number Muller C elements442 and second ports A on demultiplexer 440, each for a respective oneof the memories. In this case, additional AND gate 64, read flip-flop 62and OR gate 60 are provided for each memory. A further AND gate isprovided that inputs the output signals from all of the OR gates 60. Theoutput of the further AND gate is input to the AND gate 444 and toadditional inputs of the Muller C-elements so that rising pulses arepassed from these C elements and the AND gates only if all OR gatesindicate that either the previous operation was not a read access orthat the access memory is ready.

FIG. 7 shows an embodiment with a plurality of memories 70 a–c. Theprocessor 10 has separate ports 72, 74 for write data and read data.Similarly, the memories 70 a–c have separate ports for write and readdata. A read data multiplexer is provided between read data ports of thememories 70 a–c and the read port of the processor 10. This multiplexer76 passes the read data from the accessed memory to the processor 10.The multiplexer 76 may be controlled for example by the outputs of readflip-flops for the different memories, since these flip-flops indicatewhich of the memories was read in the previous cycle. But of course manyother ways of controlling the muliplexer may be used, for example aselection register that stores the se1 signal for the previous cycle maybe used to control the multiplexer instead.

It will be appreciated that the circuits described are merely examplesof the circuit according to the invention. For example, withoutdeviating from the invention the use of the signal levels of part or allof the circuits may be inverted. In conjunction with this the locallysynchronous circuits might be clocked by the output of the delay line.The necessary inversion to cause an oscillation through the delay linemight be provided in the handshake circuit. Neither is the inventionlimited to the particular type of handshake protocol that was used byway of example. Other handshake protocols, using for example a greateror smaller number of handshake lines may be used.

As shown the locally synchronous circuit module 10 communicates with asecond circuit 12, which may be a memory. The second circuit may be anasynchronous circuit, or it may be a locally synchronous circuit itself,operating under control of a clock oscillator circuit whose delay pathis rerouted through the handshake interface with circuit module 10.Thus, a common clock oscillator circuit is formed during the handshake.

FIG. 8 shows a circuit with a plurality of locally synchronous circuitmodules 80 a–c, each with its own clock oscillator circuit 81 a–c. Thelocally synchronous circuit modules 80 a–c all have access to the secondcircuit 82 via the same port of the second circuit. Each locallysynchronous circuit module has its own handshake interface 84 a–cbetween the locally synchronous circuit module 80 a–c and the secondcircuit 82. An arbiter circuit 88 is included between the handshakeinterfaces 84 a–c and the second circuit 82. A multiplexer and/ordemultiplexer 86 is included between the information exchange interfacesof the locally synchronous circuit modules 80 a–c and the second circuit82. A multiplexer and/or demultiplexer 86 is controlled by the arbiter88.

In operation locally synchronous modules 80 a–c are coupled to secondcircuit 82 one at a time. At such time the coupling between the outputand the input of the delay line in its clock circuit is rerouted via ahandshake interface 84 a–c with the second circuit 82 and the handshakesignals flow through the delay line.

Each locally synchronous module 80 a–c can cause the coupling betweenthe output and the input of the delay line in its clock circuit to bererouted via a handshake interface with the second circuit 82. Thearbiter 88 passes the handshake signals between the second circuit 82and the handshake interface 84 a–c of the relevant locally synchronouscircuit module 80 a–c. If another one of the locally synchronous circuitmodules 80 a–c attempts to start a further handshake with the secondcircuit while a earlier handshake is in progress, the arbiter 88 passesthe further handshake to the second circuit 82 only when the earlierhandshake has been completed. This may be done for example byacknowledging the request of the further handshake only when the earlierhandshake has been completed. When two or more locally synchronouscircuit modules 80 a–c attempt to access the second circuit at the sametime the arbiter selects one of these circuit modules 80 a–c and passesthe handshake of this circuit module first. Arbiter 88 causesmultiplexer and/or demultiplexer 86 to connect the information exchangeinterface of second circuit 82 to the information exchange interface ofthe circuit module 80 a–c whose handshake its passes. Arbiter circuitsfor passing asynchronous handshakes are known per se.

In another embodiment memories (e.g. latches and/or flip-flops) may beprovided, each between a respective one of the locally synchronouscircuit modules 80 a–c and the multiplexer and/or demultiplexer 86.Information that is exchanged between the locally synchronous circuitmodules 80 a–c and the second circuit 82 is stored during the handshake,for example in response to a request signal from the relevant locallysynchronous circuit module 80 a–c. This has the advantage that thearbiter can acknowledge the handshake from the locally synchronouscircuit module 80 a–c before the second circuit 82 has responded. Inthis case the arbiter 82 initiates a separate handshake with the secondcircuit 82, to exchange the information from the memory when theseparate handshake is answered by the second circuit 82.

A more complicated design is preferably used in case of overlaidinformation exchange, such as if second circuit 82 is a memory thatinputs an address in the same cycle in which it outputs read data for aprevious address. In this case an exchange module is preferably added tothe circuit of FIG. 8.

FIG. 9 shows an exchange module for use in such a circuit. The exchangemodule contains a first register 90, a second register 92, a repeater 94and a sequencer 96. The repeater 94 and the sequencer 96 areconventional asynchronous circuit components. Basically, the repeater 94repeatedly starts a handshake and when that handshake has been finished,it starts another handshake and so on indefinitely. Sequencer 96 startsa handshake at its left-hand port when sequencer 96 receives a requestsignal from the repeater 94 and sequencer 96 starts a handshake at itsright-hand port when the handshake at the left-hand port isacknowledged. When the handshake at the right-hand port has beenacknowledged sequencer 96 acknowledges the handshake from the repeater92.

The first register 90 stores addresses for the memory in response toacknowledge signals from the left-hand port. The second register storesread data from the memory in response to acknowledge signals from theright-hand port.

In an embodiment an exchange module of this type is included betweeneach of the locally synchronous modules 90 a–c on one hand and thearbiter 88 and the multiplexer and/or demultiplexer 86 on the otherhand.

The exchange module makes the combination of the memory, multiplexerand/or demultiplexer 86 and arbiter 88 appear to each locallysynchronous circuit module 90 a–c as if it was a memory that was notshared with other locally synchronous circuit modules 90 a–c. Theexchange module acknowledges requests from the locally synchronouscircuit module 80 a–c, it stores the corresponding address in the firstregister 90 and starts a handshake towards the memory 92. At a nexthandshake the locally synchronous circuit module 80 a–c is acknowledgedonly when the memory has acknowledged the handshake that was started inresponse to the preceding handshake. At that time the data read inresponse to the preceding address is available in the second register.

Thus, by using the embodiments of the locally synchronous modules 90 a–cand their handshake interface are of FIG. 4 and/or 6, the locallysynchronous module 90 a–c can operate at maximum speed when it does notneed to access memory and its clock signal is delayed by a minimumamount when it accesses memory. If the memory is much faster than one ormore of the locally synchronous circuit modules 80 a–c, the locallysynchronous circuit module 80 a–c are hardly delayed by the fact thatthey share the same memory, because the handshake between the exchangemodule and the locally synchronous circuit module can be completedbefore the arbiter has granted access. Write operations need not waitfor the return of data with a next handshake.

Of course, the locally synchronous modules 90 a–c and their handshakeinterfaces may have multiple ports, as shown in FIGS. 4 and 6. In thiscase multiple memories each possibly shared to a greater or lesserextent may be connected in parallel via different ports. Thus no delayoccurs in the clock signals when the locally synchronous modules 90 a–cand their handshake interfaces access different memories. Similarly someof the ports may mutually connect the locally synchronous modules 90 a–cand their handshake interfaces. Thus no memory is needed forcommunication between the locally synchronous circuit modules 90 a–c andno delay is occurred due to the memory.

1. A digital electronic circuit comprising: a locally synchronouscircuit module with a clock input and storage elements, the clock inputbeing used to time storage of information transferred between thestorage elements in the locally synchronous circuit module; a delaycircuit having an input and output coupled to the clock input, the delaycircuit providing a delay which when incorporated in a clock oscillatorensures a clock period that is at least as long as needed to transferinformation between the storage elements; a further circuit; a handshakecircuit for generating handshake signals for timing information transferbetween the storage elements and the further circuit, the handshakecircuit comprising the delay circuit, so that at least part of thehandshake signals during a handshake transaction are timed by travellingthrough the delay circuit and are applied to the clock input to clockthe locally synchronous circuit module.
 2. A digital electronic circuitaccording to claim 1, the circuit comprising a rerouting circuit forrerouting a coupling between the output and the input of the delaycircuit under control of the locally synchronous circuit module, thererouting circuit rerouting the coupling between a local path thatcauses the delay line to generate a local clock oscillationautonomously, and a handshake path that causes the delay line to passthe at least part of the handshake signals through the handshake circuitsynchronized by the further circuits.
 3. A digital electronic circuitaccording to claim 2, wherein the further circuit is arranged to operateusing temporally overlaid information exchange transactions, the localpath comprising an disabling input for disabling feedback of signaltransitions from the output to the input of the delay circuit, thedisabling input being coupled to an output of the further circuit thatdisables feedback until the further circuit has completed a final partof a last previous information exchange transaction.
 4. A digitalelectronic circuit according to claim 3, comprising an enabling circuitfor overruling disabling of the coupling via the local path by thefurther circuit before the final part of the last previous informationexchange transaction has been completed, said overruling being selectedunder control of a command signal from the locally synchronous circuitmodule.
 5. A digital electronic circuit according to claim 3, whereinthe further circuit comprises a memory with an address and datainterface coupled to the locally synchronous circuit module, the memorybeing arranged to generate a ready signal signalling that data isavailable at the same time as signalling that the memory is ready toreceive a next address, the handshake path, when active, feeding theready signal to a request input of the memory, the disabling input beingarranged to disable the local path until the ready signal indicates thatdata is available.
 6. A digital electronic circuit according to claim 2,wherein the further circuit comprises a plurality of units each with arespective handshake interface, the rerouting circuit rerouting thecoupling via a selected one of the handshake interfaces, said selectedone of the handshake interfaces being selected under control of thelocally synchronous circuit module.
 7. A digital electronic circuitaccording to claim 2, wherein the further circuit comprises a memorywith an address and data interface coupled to the locally synchronouscircuit module, the information transfer between the storage element andthe further circuit comprising transfer of an address and data, thererouting circuit routing the coupling through the handshake path whenthe locally synchronous circuit module accesses the memory andsubsequently through the local path.
 8. A digital electronic circuitaccording to claim 1, wherein the locally synchronous circuit module isone of a plurality of locally synchronous circuit modules, each locallysynchronous circuit module having its own handshake circuit and its owndelay circuit coupled to its clock input, the digital electronic circuitcomprising an arbiter and a multiplexer and/or demultiplexer coupledbetween the locally synchronous circuit modules and the handshakecircuits, the arbiter arbiting an order in which the handshaketransactions from different ones of the locally synchronous circuitmodules may progress accompanied by information exchange from thelocally synchronous circuit module via the multiplexer and/ordemultiplexer.
 9. A digital electronic circuit according to claim 8,wherein the further circuit is a memory that transfers read data inoverlaid fashion with addresses, the digital electronic circuitcomprising a respective exchange module for each locally synchronouscircuit module, the exchange module being designed to make the memoryappear as if it was not shared with any other locally synchronouscircuit module.
 10. A system component comprising: a locally synchronouscircuit module with a clock input and storage elements, the clock inputtiming storage of information transferred between the storage elementsin the locally synchronous circuit module; a delay circuit having aninput and output coupled to the clock input, the delay circuit providinga delay that is at least as large as a time interval needed fortransferring information between the storage elements; a connection forconnecting a further circuit; a handshake circuit for generatinghandshake signals for timing information transfer between the storageelements and the connection for the further circuit, the handshakecircuit comprising the delay circuit, so that at least part of thehandshake signals during a handshake transaction are timed by travellingthrough the delay circuit and are applied to the clock input to clockthe locally synchronous circuit module.